1. Field of the Invention
This invention relates to a method for preventing silicon substrate loss in fabricating a semiconductor device, and more particularly, to a method for reducing leakage current of the semiconductor device by preventing silicon substrate loss in fabricating a semiconductor device containing a periphery circuit and a memory cell.
2. Description of the Prior Art
A typical DRAM contains a periphery circuit region and a memory cell region. In fabricating a substrate is provided for fabricating the periphery circuit and a memory cell. The periphery circuit includes a row decoder, a column decoder, a refresh amplifier, a buffer, a register, a controller circuit, and a clock. The memory cell includes a transistor and a capacitor. All the forgoing devices in the memory cell region and the periphery circuit region are fabricated on the same substrate.
The leakage current of the device in the DRAM will result in serious problems such as frequent refresh operation to keep capacitors stored in capacitor of DRAM. Especially when fabricating the bit line or bit line in the memory cell region, the substrate loss is often resulted. The leakage current resulted from the substrate loss during fabricating the devices in the memory cell region is a problem caused by fabricating the semiconductor device.
As shown in FIG. 1, a gate structure 100 is formed on the substrate 101. The gate structure 100 includes the gate oxide layer 100a, a gate polysilicon layer 100b, and a gate silicide layer 100c. In addition, a control line structure 104 and a control gate structure 105 are formed on the substrate 101. Then a dielectric layer 110 is formed on the substrate, the gate structure 101, a control line structure 104, and a control gate structure 105. To form the spacer at the side-wall of the gate structure 100, an etch back process is utilized to anisotropically etch the dielectric layer 110. Because the silicon loss can not be avoided when etching the dielectric layer 110 to form the spacer, the silicon loss occurs on the whole surface of the exposed substrate 101.
Next, refer to FIG. 3, a photolithography process and an ion implantation step are subsequently used to form the source region 111 and drain region 112. When the photolithography process mentioned above is utilized to form the source and drain region in the periphery circuit region 115, a mask covering memory cell region is used to prevent the memory cell region 116 from implanting. After the forgoing step, traditional processes are utilized to fabricate the DRAM cell. Turning to FIG. 3, the gate structure 100 together with the etched dielectric layer 110 are used as the gate electrode of the transistor in the periphery circuit region 115. In the other respect, the control line structure 104 and the control gate structure 105 are in the memory cell region 116 of the substrate 101. Due to the global etching back performed to etch the dielectric layer 110, the silicon loss occurs on the exposed surface of the substrate 101 including the periphery region 115 and the memory cell region 116. Because the silicon loss occurred in the memory cell region 116, the leakage current will be resulted in the memory cell region.